Browse Prior Art Database

Overlapped Parity Check for Read/Modify/Write

IP.com Disclosure Number: IPCOM000052309D
Original Publication Date: 1981-May-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Bushaw, KA: AUTHOR [+2]

Abstract

The above circuitry provides a parity check for READ/MODIFY/ WRITE of one field in a binary word. The parity check of the write modification is accomplished without an additional parity generator. The field to be modified is forced to a predetermined condition before the modified write. The parity of this predetermined condition is known. Therefore, the parity of the modified field plus the parity of the word can be used to check whether the modified field is properly received and written.

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Overlapped Parity Check for Read/Modify/Write

The above circuitry provides a parity check for READ/MODIFY/ WRITE of one field in a binary word. The parity check of the write modification is accomplished without an additional parity generator. The field to be modified is forced to a predetermined condition before the modified write. The parity of this predetermined condition is known. Therefore, the parity of the modified field plus the parity of the word can be used to check whether the modified field is properly received and written.

The storage of the word, which is an eight-bit byte with parity, is depicted at
10. In a normal write operation, eight bits, where bits zero through three represent field one, and bits four through seven represent field two, are written from the data latches 12 into storage location 10. At the same time, parity generator 14 generates a parity bit for the word. This parity bit is passed by gate 16 into the parity bit location of storage.

In a normal read operation, the eight bits from storage location 10 are read to the data latches 12 while the parity generator 14 again generates a parity bit for the word. The generated parity bit is then compared with the parity bit from the stored location by exclusive-OR 18. Gate 16, at this time, inhibits passage of the parity bit from generator 14 to the storage location. The parity bit from storage location 10 is stored in latch 19 for possible later use in a modified write operation.

In a preconditioning write cycle, bit positions 0-3 from data latches 12 are inhibited so that only bits 4-7 of field 2 are written into the storage location 10. Field 1 is loaded in as all zeroes. Bits...