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Browse Prior Art Database

Attached Processor Interface Echo Checking

IP.com Disclosure Number: IPCOM000052329D
Original Publication Date: 1981-Jun-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Sitler, WR: AUTHOR

Abstract

In an attached processor system it is advantageous to determine that al of the control signals sent from one subsystem to the other subsystem did, in fact, arrive correctly. Generally, this interface goes across chips, modules, boards, etc., which implies cables and I/O connections. These are the least reliable components in the system and have the highest failure rates. The arrangement described herein shows how the interface lines required to control each subsystem are verified, that what was sent was indeed received. This arrangement is not limited to subsystem control but can be applied at any facility level, i.e., chip to chip, module to module, card to card, etc.

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Attached Processor Interface Echo Checking

In an attached processor system it is advantageous to determine that al of the control signals sent from one subsystem to the other subsystem did, in fact, arrive correctly. Generally, this interface goes across chips, modules, boards, etc., which implies cables and I/O connections. These are the least reliable components in the system and have the highest failure rates. The arrangement described herein shows how the interface lines required to control each subsystem are verified, that what was sent was indeed received. This arrangement is not limited to subsystem control but can be applied at any facility level, i.e., chip to chip, module to module, card to card, etc.

The application shown in the drawing is between two storage controllers. Since the interfaces from controller A to controller B and B to A are identical, the impact and cost of the design is minimal. This application also involves cables from one subsystem to the other which can result in multiple failures due to loose connections in the package. The fact that multiple failures can occur makes ordinary parity checking ineffective.

The operation of the storage controllers in an attached processor environment is as follows:
1. Instruction Processor Unit (IPU) A issues a storage request to storage controller A, and the requested data is not in controller A's cache.
2. Storage controller A then makes the request to storage controller B to determine if the data...