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Browse Prior Art Database

Controllable Process for Fabricating an LDDFET Device Using Preferential Etching

IP.com Disclosure Number: IPCOM000052340D
Original Publication Date: 1981-Jun-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Bartholomew, RF: AUTHOR [+3]

Abstract

Various techniques have been used to fabricate the lightly doped drain FET (LDDFET) devices where N regions are interposed between the heavily doped N+ source and drain regions and the P gate region. However, it may be difficult to form uniform width spacers across a wafer and to reproduce the width from run to run using reactive ion etching procedures. An alternative method of forming the narrow N regions is more controllable. The process is as follows: 1) After gate silicon dioxide layer 10 thermal growth on silicon substrate 11, a polysilicon layer 12 is deposited thereon. A Si(3)N(4) layer 13 is deposited upon layer 12. 2) Photolithography techniques are used to mask and to selectively reactive ion etch the Si(3)N(4) layer 13 everywhere but over the FET gate regions.

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Controllable Process for Fabricating an LDDFET Device Using Preferential Etching

Various techniques have been used to fabricate the lightly doped drain FET (LDDFET) devices where N regions are interposed between the heavily doped N+ source and drain regions and the P gate region. However, it may be difficult to form uniform width spacers across a wafer and to reproduce the width from run to run using reactive ion etching procedures. An alternative method of forming the narrow N regions is more controllable. The process is as follows: 1) After gate silicon dioxide layer 10 thermal growth on silicon substrate 11, a polysilicon layer 12 is deposited thereon. A Si(3)N(4) layer 13 is deposited upon layer 12. 2) Photolithography techniques are used to mask and to selectively reactive ion etch the Si(3)N(4) layer 13 everywhere but over the FET gate regions. Using the same photoresist layer 14 and the Si(3)N(4) layer 13 as a mask, the polysilicon layer 12 is reactively ion etched. 3) Ion implantation of arsenic forms the N+ source and drain regions using the photoresist layer 14 and Si(3)N(4) layer 13 to mask the polysilicon 12, as seen in Fig. 1. 4) The photoresist layer 14 is removed, and POCl(3) diffusion is made to convert the exposed polysilicon layer 12 sidewalls to N+ regions 15 of a controlled thickness, as shown in Fig. 1. 5) An etchant such as hot H(3)PO(4), which selectively etches N+ silicon, removes the N+ layer 15 and at the same time removes the Si(3)N(4)...