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Technique to Form Bipolar Transistors With Very Low Collector Resistance

IP.com Disclosure Number: IPCOM000052342D
Original Publication Date: 1981-Jun-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Anantha, NG: AUTHOR [+2]

Abstract

Diffused subcollectors are replaced by a high conductivity silicide covered by overlying laterally grown epitaxial silicon to reduce collector resistance to a very low value.

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Technique to Form Bipolar Transistors With Very Low Collector Resistance

Diffused subcollectors are replaced by a high conductivity silicide covered by overlying laterally grown epitaxial silicon to reduce collector resistance to a very low value.

A layer of metal silicide 1 (such as PtSi) is formed on p-silicon substrate 2. This can be done by depositing the metal and sintering. A fine grid of parallel grooves 3 is etched through silicide, as shown in Fig. 1. The grid spacing could be of the order of a few micrometers.

Epitaxial silicon 4 is deposited selectively in grooves 3. By adjusting the ratio of the reactant gases, little or no deposition occurs on the non-groove areas to produce the structure of Fig. 2. A suitably doped second epi 5 is grown using conditions such that preferential epitaxial nucleation occurs over the first epi 4 and that the second epi 5 propagates transversely over the non-groove areas, as shown in Fig. 3.

The buried silicide regions 1 serve as buried subcollectors. The remainder of the bipolar transistor structure is formed in the second epi 5 using conventional techniques.

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