Browse Prior Art Database

FET Logic Device

IP.com Disclosure Number: IPCOM000052353D
Original Publication Date: 1981-Jun-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 3 page(s) / 54K

Publishing Venue

IBM

Related People

Av-Ron, M: AUTHOR [+3]

Abstract

Disclosed is a one-device field-effect transistor (FET) logic device which can be operated as a latch or a three-state logic device.

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FET Logic Device

Disclosed is a one-device field-effect transistor (FET) logic device which can be operated as a latch or a three-state logic device.

Fig. 1 illustrates a conventional FET device 10 in series with a resistor R. FET 10 has its drain electrode connected to terminal VD, its gate electrode connected to terminal VG, and its substrate biased to ground potential. An appropriate pulse applied to the gate switches the device into its high conductance state which persists even after the gate voltage is subsequently reduced or returned to ground. This will be better understood by way of the following examples, in which FET device 10 is an N channel device.

Fig. 2 is a voltage/current diagram illustrating the effect of the varying levels of voltage applied to the drain and gate electrodes. As a first condition, consider the drain voltage set at VD'. (This is further illustrated in Fig. 3 which also shows the relationship of drain voltage (VD) and gate voltage (VG) to drain current (ID).) Next, apply a potential V3 to the gate. This causes drain current at the "1" level, illustrated in Fig. 3. Upon returning the gate electrode to 0 volts, the drain current increases to the "2" level, illustrated in Fig. 3. When the drain potential is returned to 0 volts, the drain current ceases.

As noted in Fig. 4, the FET device is stable in both the low resistance and the high resistance states. Thus, in the current voltage diagram of Fig. 4, the portion of the curve design...