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Minor Modifications in Standard Semiconductor Processing Allow Drastic Parasitic Substrate Current Reduction

IP.com Disclosure Number: IPCOM000052363D
Original Publication Date: 1981-Jun-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Benichou, C: AUTHOR [+3]

Abstract

This process may find application where high injection phenomena take place either in transistors or silicon controlled rectifiers (SCRs). When a PN diode is used at a high injection rate, the hole current takes advantage of the electron current and a large amount of it flows into the substrate.

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Minor Modifications in Standard Semiconductor Processing Allow Drastic Parasitic Substrate Current Reduction

This process may find application where high injection phenomena take place either in transistors or silicon controlled rectifiers (SCRs). When a PN diode is used at a high injection rate, the hole current takes advantage of the electron current and a large amount of it flows into the substrate.

To reduce the parasitic substrate current it is well known to increase the subcollector concentration (Co) maximum in order to get low resistivity, e.g., 4 Omega/[] . However, this action downgrades other parameters, such as the voltage breakdown of the transistor, mainly due to autodoping phenomenona. Therefore, in order to avoid this autodoping, it is suggested to use an epitaxy growth rate as low as .2 Mu/min.

This results in 1. a substrate current divided by 50 to 100 and thus the Beta gain of the parasitic PNPs; 2. a decrease of subcollector layer resistivity, thus reducing the V(CE) sat of a transistor or the dynamic impedance of a SCR; and
3. only a limited decrease of the voltage breakdown.

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