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Browse Prior Art Database

Binary Multiplying Arrangement

IP.com Disclosure Number: IPCOM000052372D
Original Publication Date: 1981-Jun-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 3 page(s) / 75K

Publishing Venue

IBM

Related People

Bazlen, D: AUTHOR [+4]

Abstract

This arrangement uses a simple short-cut method, by means of which two multiplier bits are simultaneously processed from left to right, beginning with the most significant and ending with the least significant multiplier bit. Alternatively, if the significant one of the two bits requires the addition of twice the multiplicand MD to the partial product, the arrangement reverts to the very simple method of processing only one MR bit at a time. This method eliminates the preparation and storage of twice the MD as well as the addition of the shifted MD to the partial product, for which purpose additional time and hardware and the addition of one bit to the data path widths and the MD register would otherwise be required.

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Binary Multiplying Arrangement

This arrangement uses a simple short-cut method, by means of which two multiplier bits are simultaneously processed from left to right, beginning with the most significant and ending with the least significant multiplier bit. Alternatively, if the significant one of the two bits requires the addition of twice the multiplicand MD to the partial product, the arrangement reverts to the very simple method of processing only one MR bit at a time. This method eliminates the preparation and storage of twice the MD as well as the addition of the shifted MD to the partial product, for which purpose additional time and hardware and the addition of one bit to the data path widths and the MD register would otherwise be required.

The multiplying arrangement shown in the figure uses only registers and data paths whose widths have not been increased. The figure shows a multiplier register MR, a partial product register consisting of a high part PH and a low part PL, and a multiplicand register MD. Addition is effected in the arithmetic and logical unit (ALU) under the control of an ADD signal. A MOVE signal is used to move the PL contents, which have been shifted by one or two bits but which are otherwise unchanged, through the ALU. A data local store (DLS) initially stores the MR and MD, and receives the final product.

Partial sums computed by the ALU are entered into the PL register, bypassing the DLS. A shifter is provided consisting of three parts SH1, SH2 and SH3 which are capable of shifting the data word received by one or two bits. After each shift, the most significant bits PL0 and PL1 are shifted from the PL register to the least significant bit positions of the PH register. A carry resulting from addition of the multiplicand to the shifted PL contents is introduced into a modifier (MOD), adding the value "1" to the shifted PH contents. The output of the modifier is connected to the input of the PH register.

For counting the necessary number of shifts during the multiplication program, a "1" is initially set in the least significant bit of the PH register. When this @1@ appears in the second most significant bit of the PH register, a loop end signal is generated if the most significant bit of the MR register is a "0" Otherwise, the loop end signal i...