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PLA Simulator

IP.com Disclosure Number: IPCOM000052377D
Original Publication Date: 1981-Jun-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Price, CA: AUTHOR

Abstract

A logic and storage circuit simulates a programmable logic array (PLA) A register holds binary values of input logic variables. A "don't care" store holds an entry for each product term or sum term, and these entries are combined with the input variables in a logic function to mask the variables that do not enter into the corresponding product or sum term. A "personalization" store holds an entry for each term, and the bits of each entry specify the matching value of each unmasked input variable and have a matching 0 bit for each masked bit of the input variables. Each output of the personality store is compared with the masked input variables to produce a match or mismatch signal for each input variable. These signals are ANDed to produce a single bit product term.

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PLA Simulator

A logic and storage circuit simulates a programmable logic array (PLA) A register holds binary values of input logic variables. A "don't care" store holds an entry for each product term or sum term, and these entries are combined with the input variables in a logic function to mask the variables that do not enter into the corresponding product or sum term. A "personalization" store holds an entry for each term, and the bits of each entry specify the matching value of each unmasked input variable and have a matching 0 bit for each masked bit of the input variables. Each output of the personality store is compared with the masked input variables to produce a match or mismatch signal for each input variable. These signals are ANDed to produce a single bit product term. The product terms are supplied to a similar circuit that simulates the OR array of the PLA and produces a single output function.

In the drawing, a register 2 holds three representative input logic variables designated A, B, and C. A "don't care" store 3 has entries for three representative product terms. The product terms are formed serially, and the three bits of one row of the "don't care" store are read for each step of the operation. Each entry has three bits corresponding to the three input variables. An AND input variable with the corresponding bit of the data unit that is read from the "don't care" store to produce a three-bit output for each product term. For example, in the fir...