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Margin of Reliability Test Employing Operating Terminals

IP.com Disclosure Number: IPCOM000052378D
Original Publication Date: 1981-Jun-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 3 page(s) / 56K

Publishing Venue

IBM

Related People

Zbrozek, JD: AUTHOR

Abstract

Memory circuits employing race comparison or "differential droop" sense are tested by a circuit driven from ;the operating inputs, the normal functions being disabled by a signal beyond the normal range. The test circuit brings the sensing clock pulse closer and closer to the originating clock pulse by an analog signal which varies an RC timing circuit.

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Margin of Reliability Test Employing Operating Terminals

Memory circuits employing race comparison or "differential droop" sense are tested by a circuit driven from ;the operating inputs, the normal functions being disabled by a signal beyond the normal range. The test circuit brings the sensing clock pulse closer and closer to the originating clock pulse by an analog signal which varies an RC timing circuit.

Representative "differential droop" sensing is illustrated in Fig. 1 in which the discharge characteristics of a reference 1 are shown in an ideal system in which the discharge characteristics of a data 1 and of a data 0 signal appear symmetrically on each side. If the higher signal 3 is assumed to be 1 data, the bottom signal 4 represents 0 data. The discharge is triggered by originating or set-up clock signal 5. The data is read as a function of difference from reference 1 at the occurrence of the sense clock signal 7. Known memory information is repetitively read while the sense clock signal is brought closer and closer to the time of the set-up signal, as shown by signals 7a, 7b and 7c. The timing at which failure occurs defines a margin of reliability of the circuit.

Fig. 2 illustrates an on-chip circuit to vary the clock times. Prior to set-up time 5, which creates a rising step-function input on line 11, FET 13 is gated on through a signal on line 15. This accomplishes pre-charge by applying operating potential +V directly through FET 13 to capacitor 17. When the set-up clock 5 goes high, FETs 19 and 21 are turned on. FET 13 is then off. The gate signal on FET 23 is an analog control signal, as will be discussed in connection with Fig. 3. Discharge of capacitor 17 is through the two parallel branches, and the effective resistance controlled by the size of the signal on the gate of FET 23 controls discharge time. When the discharge reaches a certain...