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Successful Channel Store Advance Mechanism

IP.com Disclosure Number: IPCOM000052396D
Original Publication Date: 1981-Jun-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 3 page(s) / 51K

Publishing Venue

IBM

Related People

Capowski, RS: AUTHOR [+2]

Abstract

In contemporary large-scale data processing systems (e.g., IBM System/ Models 168 and 3033) communications from a bus control network associated with system main storage to the I/O channels of the system are carried over a parallel bus shared by a plurality of channels (up to 16 channels in the 3033 systems). This bus is operated presently in response to both Fetch (storage output) requests and Store (storage input) requests originated by the channels. In response to Fetch requests, multiple bytes of data (up to 8 bytes in the 3033 systems) are extracted from main storage and transferred in parallel via the bus to a designated one of the sharing channels.

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Successful Channel Store Advance Mechanism

In contemporary large-scale data processing systems (e.g., IBM System/ Models 168 and 3033) communications from a bus control network associated with system main storage to the I/O channels of the system are carried over a parallel bus shared by a plurality of channels (up to 16 channels in the 3033 systems). This bus is operated presently in response to both Fetch (storage output) requests and Store (storage input) requests originated by the channels. In response to Fetch requests, multiple bytes of data (up to 8 bytes in the 3033 systems) are extracted from main storage and transferred in parallel via the bus to a designated one of the sharing channels. In response to Store requests, the bus is used presently to indicate if exceptional/abnormal conditions have been encountered during the associated storage input operations (i.e., program exceptions or machine malfunctions).

In addition to lines for transferring data (in response to Fetch requests), the above-mentioned bus includes a line for signalling an "advance" indication to the channel in association with each discrete response to a request, lines for presenting channel identity information (CHID) designating the channel to which the associated advance/response is to be directed (such CHID information being received by the bus control network and queued in association with each request), and lines for presenting check signals denoting exception/abnormal conditions encountered during the handling of the associated request. The check signals presented in association with a successfully handled request (no exceptions encountered) all correspond to zero information, or idle line states.

It is recognized that the present indication of a successfully handled Store request, which in effect consists only of an advance indication and associated CHID information (the data and check lines being idle), constitutes a wasteful use of the bus which tends, in a disproportionate manner, to degrade system productivity and expose the channels to unnecessary overruns. As show...