Browse Prior Art Database

Fast Send Count

IP.com Disclosure Number: IPCOM000052404D
Original Publication Date: 1981-Jun-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Frye, HE: AUTHOR

Abstract

The operation of send count and receive count instructions is describe in U.S. Patent 4,177,513, beginning on column 23, line 12 and ending on column 25, line 10. During operation of a send count instruction, if the count is greater than or equal to the limit, remove cycles are taken so as to dequeue waiting task dispatching elements (TDEs) from the counter and enqueue them to the task dispatching queue (TDQ). Once this is accomplished, the dispatch cycles are activated and a task switch occurs whereby, assuming that the highest priority waiting TDE becomes the highest priority TDE on the TDQ, control is then returned to the previously unsatisfied receive count instruction of that TDE.

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Fast Send Count

The operation of send count and receive count instructions is describe in U.S. Patent 4,177,513, beginning on column 23, line 12 and ending on column 25, line 10. During operation of a send count instruction, if the count is greater than or equal to the limit, remove cycles are taken so as to dequeue waiting task dispatching elements (TDEs) from the counter and enqueue them to the task dispatching queue (TDQ). Once this is accomplished, the dispatch cycles are activated and a task switch occurs whereby, assuming that the highest priority waiting TDE becomes the highest priority TDE on the TDQ, control is then returned to the previously unsatisfied receive count instruction of that TDE. The receive count instruction for that TDE would be satisfied, however, because the send count instruction was only for that TDE; the other TDEs which were removed from the counter and enqueued onto the TDQ would not have their receive count instruction satisfied when they become the highest priority task on the TDQ. Instead, their receive count instruction will result in remove cycles, whereby the TDE on the TDQ is returned to the send-receive counter (SRC) from which it came. Thus, there are a number of unproductive task switches which occur; i.e., the TDEs are moved from the counter to the TDQ and from the TDQ back to the counter.

The present arrangement provides an improvement whereby only the TDE,
i.e. the highest priority waiting TDE on the SRC counter for whi...