Browse Prior Art Database

Buffer Memory Addressing

IP.com Disclosure Number: IPCOM000052416D
Original Publication Date: 1981-Jun-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 3 page(s) / 45K

Publishing Venue

IBM

Related People

MacLean, NH: AUTHOR

Abstract

"Wrap bits" in an address field dynamically determine the size of a buffer segment to be used, while address bits more significant than the wrap bits select location of the segment in the buffer.

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Buffer Memory Addressing

"Wrap bits" in an address field dynamically determine the size of a buffer segment to be used, while address bits more significant than the wrap bits select location of the segment in the buffer.

A buffer memory is interposed between a plurality of hosts via a channel C and a plurality of devices via an interconnection D. A microcomputer controls and monitors the signal transfers between the host and the buffer and between the devices and the buffer; such transfers are independent and can be concurrent. The status and control of the buffer is set forth in the directories associated with the micro computer. Each segment of the buffer memory has a single entry in the directory which corresponds to the horizontal lines in Fig. 1. When each of the buffer segments is active, the buffer segment is associated with a particular device as indicated in column DEV, which contains a device address. The size of the segment, and its highest address, is set forth in the column EX which identifies the extent of the memory segment. The LOW column indicates the starting address of the record within a segment, while the HIGH column indicates the ending address of the record in the segment to be transferred. If there are a plurality of records in each segment, for each segment there will be a plurality of entries in each of the LOW and HIGH columns.

A channel transfer over C is initiated by a host selecting a device by informing the microcomputer. The microcomputer then transfers the signals from the directory entry relating to that device, such as device B, to a programmable logic array (PLA) for controlling addressing of the buffer memory. The entry associated with device B is addressed by the device address. The gating network transfers the extent content "1" to the channel wrap register (CWR); CWR cooperates with the channel pointer address register (CP) which receives the low address "X1+1" from the directory. The signal contents of CWR are forced upon the higher order of bit positions of CP such that these bits indicate the highest address range of the buffer segment, i.e., the CWR bits truncate the CP counting to yield a buffer segment highest address in accordance with the CWR bit pattern. Incrementing CP by 1 causes the lower portion of CP to go count the registers in the segment. The bits forced into CWR in this manner cause each segment to become an independently completely automatic addressable segment, with the size of the segment determined by the CWR bit pattern.

The contents of the HIGH column are transferred to the channel stop register (CS) "X3" which indicates the last byte of the record to be transferred. The contents of CP and CS are compared to supply an "end" signal to the microcomputer. For stoppi...