Browse Prior Art Database

Loop Station Adapter Synchronization

IP.com Disclosure Number: IPCOM000052433D
Original Publication Date: 1981-Jun-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 61K

Publishing Venue

IBM

Related People

Heasman, BR: AUTHOR

Abstract

In attaching a terminal, such as an IBM 8775 display to a loop a probl exists in ensuring correct synchronization between the operation of the terminal data link controller (DLC) and the loop. The solution described in this article takes advantage of the SDLC (Synchronous Data Loop Control) architecture, which allows the 0 of a previous flag byte to be used in the succeeding flag byte.

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Loop Station Adapter Synchronization

In attaching a terminal, such as an IBM 8775 display to a loop a probl exists in ensuring correct synchronization between the operation of the terminal data link controller (DLC) and the loop. The solution described in this article takes advantage of the SDLC (Synchronous Data Loop Control) architecture, which allows the 0 of a previous flag byte to be used in the succeeding flag byte.

Fig. 1 illustrates the problem showing that the loop station adapter (LSA) generates a corrupted flag of between 1-6 bits.

The synchronizing of the DLC transmit data is achieved by changing the Tx clock into the DLC chip from Tx clock to (Tx clock + (RTS.CTS.TxDATA)). This then stops the clock when Request to Send (RTS) has been activated and when a zero bit is shifted out of the DLC chip prior to the receipt of Clear to Send (CTS).

When CTS goes active, the Tx clock is restarted and the first bit presented to the LSA is the second bit of the flag. This then conforms to SDLC architecture, as is shown in Fig. 2. Fig. 3 shows in block terms the components used.

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