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On Board Logic for Multi Dot Thermal Printhead

IP.com Disclosure Number: IPCOM000052455D
Original Publication Date: 1981-Jun-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 4 page(s) / 125K

Publishing Venue

IBM

Related People

Mizzi, JV: AUTHOR

Abstract

This article relates generally to thermal printheads and, more particul to multi-dot thermal printheads which also carry the logic used for energizing the individual dots. Still more particularly, the article relates to a general interface which permits rapid control of any dot using only four lines. Logic including a shift register is integrated on a wide (e.g., 8 1/2") multi-dot (e.g., 2000 dots) printhead.

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On Board Logic for Multi Dot Thermal Printhead

This article relates generally to thermal printheads and, more particul to multi-dot thermal printheads which also carry the logic used for energizing the individual dots. Still more particularly, the article relates to a general interface which permits rapid control of any dot using only four lines. Logic including a shift register is integrated on a wide (e.g., 8 1/2") multi-dot (e.g., 2000 dots) printhead.

With the advent of LSI technology, complex repetitive logic structures are simple to implement. The scale of integration is low density, and several chips are distributed along the width of the head to facilitate wiring and heat dissipation.

Figs. 1 and 2 show top and side views, respectively, of the physical layout of the head and the associated logic/drive chips. Fig. 1 shows a top view of thermal printhead 1 with seven integrated circuit chips 2 mounted thereon. Hot dots (not shown) are disposed on the opposite side of head 1 and are interconnected to chips 2 via lines 3 on a one line per dot basis. Control lines including SR Clock, Set, Reset and Voltage are connected in parallel to each of the chips 2.

Fig. 2 shows a cross-sectional, side view of thermal printhead 1 which includes an aluminum heat sink 4 and regions 5 of thermal jelly surrounding chips 2.

Fig. 3 shows a partial schematic, partial block diagram of the logic used to control the heating of the thermal head dots 6. A shift register 7 having one cell per thermal head dot is of the serial-in/ parallel-out type which propagates a single "1" bit from left to right in Fig. 3 each time the shift register clock SR Clock is pulsed. Shift register 7 is shown controlling the fifth thermal dot 6 in Fig. 3. The energizing of each dot 6 requires one AND gate 8 per dot and one Set/Reset Latch Driver 9 per dot. In operation, if the Set line is pulsed at the instant shown in Fig. 3, Driver 9 associated with the fifth thermal dot 6 is set. When a scan of shift register 7 is completed, the Voltage Return line is pulsed to ground and the fifth dot 6 and any other dots connected to drivers 9 latched in the ON condition will heat up. The Reset line is energized preparatory to a new scan of shift register 7.

Fig. 4 shows a block diagram of interface logic for a digital interface to simulate the operation of a three-channel strip chart recorder with print capability. The interface arrangement of Fig. 4 operates as follows assuming that the chart paper has just been stepped to a new line. (a) The Microcomputer loads Start Plot Location into the System Location Register via Data Base (or where plot left off in last paper location) for Plot Channel 1. (b) The Microcomputer loads Magnitude of Number of Plot steps for this paper location into the Delta Counter. If delta is negative, it also subtracts this amount in the System Location Register and turns Plot line ON. (c) The Microcomputer removes Inhibit from the Shift Register Clock. (d)...