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Browse Prior Art Database

Complementary Dynamic Memory Cell

IP.com Disclosure Number: IPCOM000052461D
Original Publication Date: 1981-Jun-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 6 page(s) / 108K

Publishing Venue

IBM

Related People

Chao, HH: AUTHOR [+4]

Abstract

A semiconductor memory cell is described herein which is a modification of the non-destructive read-out dynamic memory cell described in U.S. Patent 4,085,498. The memory cell in U.S. Patent 4,085,498 depends on avalanche breakdown or punch through which is difficult to control and may introduce reliability problems; hence, it is desirable to write the memory cell with other methods. Therefore, a write gate has been added to the memory cell. This write gate controls a hole current path, which is underneath the memory gate, from the substrate to the hole storage region. Thus, a more controllable and reliable method for writing the memory cell to "on" or "off" state is obtained.

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Complementary Dynamic Memory Cell

A semiconductor memory cell is described herein which is a modification of the non-destructive read-out dynamic memory cell described in U.S. Patent 4,085,498. The memory cell in U.S. Patent 4,085,498 depends on avalanche breakdown or punch through which is difficult to control and may introduce reliability problems; hence, it is desirable to write the memory cell with other methods. Therefore, a write gate has been added to the memory cell. This write gate controls a hole current path, which is underneath the memory gate, from the substrate to the hole storage region. Thus, a more controllable and reliable method for writing the memory cell to "on" or "off" state is obtained. Due to the novel design of the write gate, information can be written into the selected bit on the addressed wordline without disturbing the contents of the other bits on the same wordline (hereupon this feature is called X-Y addressed write operation). Thus, the read operation in the normal write cycle of the dynamic RAM (random- access memory) can be eliminated.

A possible layout of this complementary dynamic memory cell is shown in Fig. 1, which also shows the cross-sectional lines for Figs. 2 and 3. The cell size is very small because only half contact is required for each cell. The fabrication is basically a standard double level polysilicon gate FET process except that it requires two additional process steps are as follows:

Before first polysilicon disposition:

1. A photoresist mask is required to define the area for the n-type ion implant.

2. N-type ions are implanted to part of the write gate region. The n-layer formed by this ion implant serves as the substrate of the p channel FET. The part of the write-gate region which is masked from receiving this n-type ion implant is the source of this p-channel FET.

3. Another photoresist mask is required to define the area for shallow p-type ion implant.

4. P-type ions are implanted to part of the write-gate region. Due to this shallow p-type ion implant, the V of the p-channel FET has been shifted to positive voltage. Thus, the use of negative gate bias can be avoided.

B. Before second polysilicon deposition:

1. N-type ions are implanted to the memory-gate region to form the buried n- channel.

2. P-type ions are implanted very shallow to form a thin p-layer underneath the memory gate. This provides a hole storage capability with zero gate bias.

The functions of the memory FET and the read operation of the memory array described in U.S. Patent 4,085,498 are not affected by this modification; therefore, they will not be repeated here.

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The functions of the write gate are as follows: The n-layer is used to connect the drain and the buried n-channel of the memory FET and should not be totally depleted at all operation conditions. This N-layer also serves as the substrate of the depletion-mode p-channel FET underneath the write gate. The doping level of the n-layer...