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LSSD Compatible Scheme for Creating Clocks Having Pulse Widths Which Are Less Than That Transmittable on TCMs

IP.com Disclosure Number: IPCOM000052474D
Original Publication Date: 1981-Jun-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 5 page(s) / 96K

Publishing Venue

IBM

Related People

Black, CM: AUTHOR [+2]

Abstract

Since the minimum clock pulse transmittable on a TCM (Thermal Conductin Module) is expected to be larger than that demanded by future systems with small cycle times, there may soon be a need for a clock generation scheme capable of creating faster clocks. The following describes an LSSD (Level Sensitive Scan Design)-compatible scheme for generating on chip clocks (by "clock chopping" which run at twice the frequency of the off-chip clocks. The cost of such a clock generation scheme is 19 OR/NOR gates, 1 SXL (Shift-Register Latch), 1 I/O Pin, and the writing of 1 chip test test-case.

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LSSD Compatible Scheme for Creating Clocks Having Pulse Widths Which Are Less Than That Transmittable on TCMs

Since the minimum clock pulse transmittable on a TCM (Thermal Conductin Module) is expected to be larger than that demanded by future systems with small cycle times, there may soon be a need for a clock generation scheme capable of creating faster clocks. The following describes an LSSD (Level Sensitive Scan Design)-compatible scheme for generating on chip clocks (by "clock chopping" which run at twice the frequency of the off-chip clocks. The cost of such a clock generation scheme is 19 OR/NOR gates, 1 SXL (Shift-Register Latch), 1 I/O Pin, and the writing of 1 chip test test-case.

Current estimates for the minimum clock pulse-width transmittable to chips in the TCM/Clark-board configuration are about 6 to 8 ns. This certainly would be an unacceptable restriction for a high performance system in "1-micron" (or possibly even "1.5-micron" technology. There is a need for a scheme for generating faster clocks on-chip using the clocks that can be transmitted to the chips.

Clock chopping is a method for generating a pulse from either the falling or the rising edge of some input clock. Consider the circuit and timing diagrams of Fig. 1.

As can be seen by Fig. 1, this configuration of diagrams generates a pulse of duration "d" at every rising edge of the input +clock (+X means positive active; -X means negative active).

In the circuit of Fig. 2, a pulse of duration "d" will be generated at every falling edge of the +clock.

If the circuits of Figs. 1 and 2 are combined and the "delay gate" is replaced by some number of logic gates, the circuit of Fig. 3 is obtained. This circuit generates a pulse of duration "d" at both the rising and the falling edges of the input clock.

The delay "d" can be adjusted by changing the number of gates in the delay line. For gate count purposes, assume that 4 gates are used in the delay line. If the input clock is symmetric (positive and negative phases are of equal duration), this clock chopper will generate an on chip clock with equally spaced pulses of duration "d" at twice the frequency (half the period) of the input clock.

This clock chopper is entirely incompatible with LSSD.

For automatic static testing, LSSD demands a great degree of control of clocks and this scheme does not offer such control. For example, LSSD requires that the clocks be capable of being held statically at either a "0" or a "1". The output of the clock chopper, however, cannot be held at a "1" for more than "d" time units.

What can be done is to hide the clock chopper from the automatic tester by bypassing it with the input clock. By this, the entire chip becomes controlled by

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the LSSD-compatible input clock; hence, the entire chip will look LSSD- compatible during automatic testing. To hide the clock chopper, an Enable-Chop test input (primary input used for testing) is used in Fig. 4.

When the Enable-Chop l...