Browse Prior Art Database

# Logic Design Simplification

IP.com Disclosure Number: IPCOM000052475D
Original Publication Date: 1981-Jun-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 1 page(s) / 12K

IBM

Roth, JP: AUTHOR

## Abstract

In the design and testing of logic several complex algorithms are brought into play. Here three techniques simplifying some of these operations are described.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 63% of the total text.

Page 1 of 1

Logic Design Simplification

In the design and testing of logic several complex algorithms are brought into play. Here three techniques simplifying some of these operations are described.

The first technique is an extension and at the same time simplification of the P* process [*] for reducing regular logic in its acyclic portions to two-level equivalents' The difficulty encountered with P* is that for large designs, the size of the two-level equivalent circuits becomes very excessive. Here, as the P* process is being unfolded, changing many levels to two levels, a count is kept on the size of the arrays being formed; when this count exceeds a bound specified by the user, the process is terminated locally, the portion of the design thus far reduced is rendered in the final transformation as its own two-level form, and its inputs are treated as outputs for the operation of P* on subsequent portions of the circuit. In this manner large designs can always be rendered into assemblages of two-level designs, depending upon the user, for subsequent processing such as factoring and implementation [*]. This process is termed dynamic partitioning.

In optimizing logic [*], a critical step is the determination of redundancy with respect to a cover (a PLA). This is used as in approximations, such as SHRINK.

The following (second) method is a substantial improvement over previous methods.

Let e be a cube and E = [e1, ..., er], a set of cubes; then e is redundant with respect to...