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Browse Prior Art Database

Signal Transition Detection Circuit

IP.com Disclosure Number: IPCOM000052494D
Original Publication Date: 1981-Jun-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 4 page(s) / 87K

Publishing Venue

IBM

Related People

Cannon, JW: AUTHOR [+2]

Abstract

This circuit detects a signal transition point using clocked level sensitive scan design (LSSD) latches. A single shift register latch (SRL), instead of multiple SRLs, is used to detect a signal transition point.

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Signal Transition Detection Circuit

This circuit detects a signal transition point using clocked level sensitive scan design (LSSD) latches. A single shift register latch (SRL), instead of multiple SRLs, is used to detect a signal transition point.

Level sensitive scan design ground rules specify that all storage elements are to be implemented as clocked DC latches. The LSSD latches are organized as shift register latches. A single DC clocked Set/Reset SRL can be used as an edge triggered storage device and still satisfy the LSSD ground rules.

Fig. 1 shows the edge triggered circuit which includes latches L1 and L2 and associated logic. Latch L1 is expanded in Fig. 2, and latch L2 is expanded in Fig. 3. Latch L1 of the SRL is a Set/Reset latch during system mode and a polarity-hold during scan mode. Latch L2 of the SRL is a polarity-hold latch in both scan and system modes.

In Fig. 1, the latch L2 outputs are shown connected to latch L1 inputs The latch L1 outputs cannot be used to provide the necessary feedback since LSSD rules do not permit use of the latch's outputs to drive its own inputs.

For the circuit in Fig. 1 to operate as an edge triggered latch, the clocking scheme has certain requirements (see Figs. 4 and 5). The A-scan clock line must be held off during system mode. With the A-scan clock off, the scan input is disabled.

The system clock and the B-scan clock lines are both free-running pulses and non-overlapping with respect to each other. This clocking scheme insures that latch L2 outputs are stable (which are some of the L1 inputs) while latch L1 is being clocked and vice versa. The L2 clock is gated by the edge trigger input signal and the plus L1 output. If either the edge trigger input signal is inactive (which is minus in this case) or the latch L1 is reset (which makes the positive output minus) or both, the clocking of latch L2 by the B-scan clocking pulses is enabled. If both the edge trigger input signal is active and latch L1 is set, the clocking for latch L2 is disabled and the state of latch L2 is frozen.

Depending on the state that is stored in latch L2, which is being fed back to latch L1, latch L1 is either a Set Only flip-flop or a Reset Only flip-flop. If the latch L2 outputs are in a reset state, the reset input port is disabled. Latch L1 can only go in the set direction. No change will occur to the L1 latch if the set input is inactive while the latch L2 is reset. If latch L2 is in the set state, the edge trigger input signal is degated. Latch L1 can go in the reset direction only.

The circuit in Fig. 1 is a nega...