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Time Out Restart Circuitry for Overlapped Control Read Only Storage

IP.com Disclosure Number: IPCOM000052495D
Original Publication Date: 1981-Jun-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 4 page(s) / 109K

Publishing Venue

IBM

Related People

Cannon, JW: AUTHOR [+2]

Abstract

A three-phase overlapped read-only Storage (ROS) used in a processor is allowed to time-out and restart in the proper sequence without requiring an excessive number of storage elements. The circuitry is useful when interfacing with any ROS that has maximum active times specified on its chip select lines. It is particularly useful if the application has any type of overlapped ROS which must have the ability to stop for indefinite times.

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Time Out Restart Circuitry for Overlapped Control Read Only Storage

A three-phase overlapped read-only Storage (ROS) used in a processor is allowed to time-out and restart in the proper sequence without requiring an excessive number of storage elements. The circuitry is useful when interfacing with any ROS that has maximum active times specified on its chip select lines. It is particularly useful if the application has any type of overlapped ROS which must have the ability to stop for indefinite times.

In a representative application, a processor interfaces with three banks of 4K x 36-bit ROS to provide a time-out/restart function to an interleaving ROS cycle design. In high speed operation, the ROS typically requires approx. 300 nanoseconds for access and approx. 150 nanoseconds for re yielding an approx. 450-nanosecond total cycle time. Spacing accesses apart by approx. 150 nanoseconds allows a processor to operate three times as fast as the ROS it interfaces with, as seen in Fig. 1. Another requirement of the ROS is that no access may last longer than one microsecond, which may be exceeded due to interlocking situations between the processor and the input/output channel. The hardware interface described provides a time-out and restart sequence of events that preserves the execution order of the microcode instructions.

The three phases of the three ROS interleaving scheme are X, Y, and Z cycles, and are executed in that order. Referring to Fig. 1, it is noted that there are always two accesses in progress in any one cycle. In the case of an interlock, the processor remains in the cycle it is in at the time. If the accesses in progress finish while the processor is still interlocked, the interface terminates the access and holds the ROS data at the outputs of the ROS. When the processor is allowed to continue, the interface does not allow a new access to the ROS until the data from the previous access has been applied to the processor in its relative cycle. This technique insures against destroying the ROS data due to a partially complete access. The interface must be able to provide this sequence regardless of which cycle the processor stops in.

Fig. 2 shows the basic organization of the interface. Each of the three ROS banks has a dedicated counter-decoder combination that provides the necessary signals to access the ROS. Each counter-decoder combination is synchronized with the counter-decoder associated with the previous cycle to insure the proper restart sequence. The operation of the counter is shown in Fig. 3. When driven by an approx. 20-megahertz oscillator, each count consists of an approx....