Browse Prior Art Database

Stop on Address Operation

IP.com Disclosure Number: IPCOM000052496D
Original Publication Date: 1981-Jun-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 3 page(s) / 49K

Publishing Venue

IBM

Related People

Cannon, JW: AUTHOR [+2]

Abstract

The Stop On Address (SOA) scheme described here eliminates masking out of software problems which are being diagnosed by microcoded SOA routines. The original problem cannot be found with such microcode SOA routines since the reduced performance of the testing mode prevents the problem's occurrence. The processor here is able to continue normal system performance when in SOA. Thus, the software problem will occur so that it can be located when in SOA mode.

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Stop on Address Operation

The Stop On Address (SOA) scheme described here eliminates masking out of software problems which are being diagnosed by microcoded SOA routines. The original problem cannot be found with such microcode SOA routines since the reduced performance of the testing mode prevents the problem's occurrence. The processor here is able to continue normal system performance when in SOA. Thus, the software problem will occur so that it can be located when in SOA mode.

A Stop On Address function provides a means of halting the processor when a previously selected and stored address is encountered. This function is used primarily for troubleshooting software programs by system programmers, field engineers and customers.

Processors such as the processor described in the manual entitled "IBM Series/1 Model 5 4955 Processor", GA34-0021-1, implement the SOA function by the addition of approximately 12 independent microcode instructions following each I-Phase Fetch. Pages 7-5 and 7-6 of that manual describe the initiation of the Stop On Address function. The microcode instructions are encountered if and only if SOA mode is invoked. Problems which occur at certain rates of operation in the normal mode do not occur when SOA is activated to locate the problem; thus, the problem does not occur when in the SOA mode that is used to locate the problem, thereby creating a paradox.

A hardware implementation of the SOA function requires no repeated independent microcode instructions as does a software version. This allows the system to perform its normal services at the same rate with and without SOA mode.

The processor described in the manual makes a microcode compare only on the I-Phase Instruction Fetch; however, much software trouble shooting centers around E-Phase Store operations. This SOA implementation allows halting on both the I-Phase Instruction Fetch operations and the E-Phase Store operations.

A block diagram of the hardware implementation is shown in the drawing. The addresses are applied the same for a Load SOA as for a memory access. A Load SOA Addresses signal on line 1 effects storage of the address bits in the SOA Register 2. No SOA Compare sigal on line 3 for AND circuit 4 is generated during a Load SOA function because the SOA Compare is strobed, or gated, via line 5 only during memory cycles and not during Load SOA.

This logic is on each increment of storage which is on the central processing unit (CPU) card and the storage increment cards. An output from the Card Select block 6 is generated by the card whose Address Set...