Browse Prior Art Database

Linked or Arrays for Nanoword Timing

IP.com Disclosure Number: IPCOM000052497D
Original Publication Date: 1981-Jun-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 22K

Publishing Venue

IBM

Related People

Kraft, WR: AUTHOR [+5]

Abstract

One problem when designing computers is how to get microwords (or nanowords) from the control logic on a timely basis and in the right sequence.

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Linked or Arrays for Nanoword Timing

One problem when designing computers is how to get microwords (or nanowords) from the control logic on a timely basis and in the right sequence.

One technique (shown in the figure) for doing this is to use a programmable logic array (PLA) which has one AND array and a plurality of OR arrays.

The OP code is decoded by the AND array, and the output of the AND array is fed to the first OR array OR1. From OR1, the first microword is provided through a driver circuit to OR2. After a delay, a microword is ready from 0R2 and so on to ORn. Each of the microwords is then applied through a multiplexer (MUX) to be used as required. For the system to work, the delay through each OR array must be no greater than the cycle time of one microword. Static delays can be designed with this in mind, or both the drivers and OR arrays could be dynamic. In the latter case, the clocks would determine proper synchronization.

In short, this circuit provides microwords in proper sequence and at reasonable speeds. Since the OR arrays are isolated from one another by drivers, they do not load each other. Hence, good speed performance is obtained. A further advantage is that only one AND array serves all the OR arrays. Unique XND arrays for each OR array are not needed.

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