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Recessed Oxide Isolation Etch Bias Improvement

IP.com Disclosure Number: IPCOM000052504D
Original Publication Date: 1981-Jun-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Frederick, R: AUTHOR [+4]

Abstract

VLSI (very large-scale integration) designs require tighter ground rule and smallest etch bias capability. Recessed oxide isolation (ROI) processing is included. This is required to achieve smaller ROI width capability, resulting in circuit density enhancement. The ROI trench is formed by etching nitride-oxide-silicon after the photoresist image has been formed by standard lithography techniques. A resist side wall slope of approximately 80 degrees is necessary to produce minimal ROI etch biases. Only then can a ROI nitride-oxide-silicon trench be processed with a single step CF(4) dry etch process, resulting in acceptable ROI etch bias. However, if the resist slopes cannot be maintained nearly vertical, then the etch bias produced with this dry processing is larger for the ROI trench, which is not acceptable.

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Recessed Oxide Isolation Etch Bias Improvement

VLSI (very large-scale integration) designs require tighter ground rule and smallest etch bias capability. Recessed oxide isolation (ROI) processing is included. This is required to achieve smaller ROI width capability, resulting in circuit density enhancement. The ROI trench is formed by etching nitride-oxide- silicon after the photoresist image has been formed by standard lithography techniques. A resist side wall slope of approximately 80 degrees is necessary to produce minimal ROI etch biases. Only then can a ROI nitride-oxide-silicon trench be processed with a single step CF(4) dry etch process, resulting in acceptable ROI etch bias. However, if the resist slopes cannot be maintained nearly vertical, then the etch bias produced with this dry processing is larger for the ROI trench, which is not acceptable. The larger etch bias is due to the etch rate of the photoresist plus the extended etch time required for silicon etching. After oxidation ROI widths are wider, and device windows become smaller. The design ground rules are violated and device failures may occur, significantly reducing the reliability.

The dry-wet etch hybrid process for the ROI trench formation followed by the subsequent ROI oxidation results in the desired narrower ROI widths, satisfying the ground rule requirements. After the photoresist image is formed, then the silicon nitride and oxide are etched with the diode CF(4) dry etch (RIE) proces...