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Complementary Bipolar FET Integrated Circuit

IP.com Disclosure Number: IPCOM000052520D
Original Publication Date: 1981-Jun-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 5 page(s) / 174K

Publishing Venue

IBM

Related People

Dorler, JA: AUTHOR [+3]

Abstract

The drive restrictions of MOS devices severely limit their performance; low current, high impedance drive capability results in large resistance-capacitance (RC), time constants. The ability to use bipolar devices, PNP and NPN, both internally and, specifically, as drivers has been shown to improve the overall performance by a factor of more than two times. This is particularly important in the area of arrays, or even main memory, where high capacitive nets, both on and off the chip, are the rule rather than the exception. Bipolar devices have drive impedances measured in the tens of ohms as compared to FET devices which are measured in kilo-ohms.

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Complementary Bipolar FET Integrated Circuit

The drive restrictions of MOS devices severely limit their performance; low current, high impedance drive capability results in large resistance-capacitance (RC), time constants. The ability to use bipolar devices, PNP and NPN, both internally and, specifically, as drivers has been shown to improve the overall performance by a factor of more than two times. This is particularly important in the area of arrays, or even main memory, where high capacitive nets, both on and off the chip, are the rule rather than the exception. Bipolar devices have drive impedances measured in the tens of ohms as compared to FET devices which are measured in kilo-ohms.

This article describes a process and structure to include an isolated vertical NPN and an non-isolated PNP bipolar device on FET integrated circuit structures. The process and structure are as follows: a) Initial silicon dioxide (SiO(2)) layer 10 and silicon nitride (Si(3)N(4)) layer 11 deposition on P- substrate 8. b) Mask with photoresist layer 12 for the recessed oxide isolation (ROX areas), receive ion etch (RIE) of the Si(3)N(4), SiO(2) and Si to form trenches 14. c) The field boron ion implant of 1.75 x 10/13/ cm/-2/ and 100 KeV forms P region 13 at the bottom of the trenches 14, as shown in Fig. 1. d) Photoresist mask 12 is removed, and ROX oxidation of about 6400 angstroms is effected. e) Si(3)N(4) layer 11 is stripped and silicon dioxide layer 10 is stripped to produce the Fig. 2 structure. f) Gate silicon dioxide layer 15 is grown to about 450 angstroms in thickness. g) Blockout mask 16 for NPN's collector phosphorous Pion implant at 100 KeV is formed, and the ion implant accomplished to form N regions 17, as shown in Fig. 3. h) Blockout mask 18 for PNP's collector is formed and boron /11/B+ implant 1.75 x 10/13/ cm/-2/ at 100 KeV is accomplished to form P regions, as shown in Fig. 4. i) Blanket V(t) adjustment for enhancement FET using /11/ implant
5.7 x 10/11/ cm/-2/ at 70 KeV causes formation of P regions 20, as shown in Fig. 5. j) Blockout mask 21 for depletion device V(t) adjustment and arsenic /75/As implant 2 x 10/12/ cm/-2/ at 80 KeV forms N regions 22, as seen in Fig. 6. k) PNP base, buried contact photoresist mask 23 is formed, and the silicon dioxide layer 15 is removed in the base and buried contact regions, as shown in Fig. 7. l) The first polysilicon layer 23 is deposited with 4000 angstroms thickness and phosphorous doping. A chemical...