Browse Prior Art Database

Bit Current Steering Network

IP.com Disclosure Number: IPCOM000052523D
Original Publication Date: 1981-Jun-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 78K

Publishing Venue

IBM

Related People

Marcello, V: AUTHOR [+3]

Abstract

This bit current steering network is suitable as the final stage of the bit address scheme in a Harper cell array matrix. A reduced cross-section of this network is shown in Fig. 1. Inputs to the network are from the bit decoders and the word line.

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Bit Current Steering Network

This bit current steering network is suitable as the final stage of the bit address scheme in a Harper cell array matrix. A reduced cross-section of this network is shown in Fig. 1. Inputs to the network are from the bit decoders and the word line.

For ease of explanation, the bit current steering network of Fig. 1 has been divided into three distinct parts: 1. Read-Write constant current sources 2. Bit current switch (driven from 1/16 select bit decode) 3. Restore network (including: Schottky Barrier Diodes (SBDs), restore transistors and level shifter)

The read-write constant current source determines the current to be steered to the selected bit rails by means of the bit current switch. Because the read-write current has been diverted from the de-selected bit rails, these rails will tend to go to a hanging potential. However, current is pulled from the bit rails through restore SBDs (Approximately 25 MuA/ to the restore current source, and the bit rail potential is thus defined. The amount of voltage swing on the bit rails from selected to de-selected states can be controlled by adjusting the level shift voltage. The current flow from the bit lines during both states is further discussed with reference to Figs. 2 and 3.

Selected Mode: The two bit rails in a selected mode are shown in Fig. 2. Transistors 5 and 7 provide the read-write current to the selected bit rails. Transistor 6 disables transistors 1 and 2 by dropping about 1 vo...