Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Paging from Multiple Bit Array Without Distributed Buff

IP.com Disclosure Number: IPCOM000052527D
Original Publication Date: 1981-Jun-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 4 page(s) / 83K

Publishing Venue

IBM

Related People

Aichelmann, FJ: AUTHOR

Abstract

A technique is described whereby a multiple bit output array chip transfers its output at a single transfer without requiring distributed logic buffering. The transferred bits are then distributed across different ECC (error correcting code) words via address selection of different locations in the full page buffer of the array controller.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 53% of the total text.

Page 1 of 4

Paging from Multiple Bit Array Without Distributed Buff

A technique is described whereby a multiple bit output array chip transfers its output at a single transfer without requiring distributed logic buffering. The transferred bits are then distributed across different ECC (error correcting code) words via address selection of different locations in the full page buffer of the array controller.

Paging store applications utilize memories which must supply multiple data transfers to accommodate or satisfy the page request. In such memory systems utilizing multiple bit output chips, the chip outputs cannot simultaneously be used within the same data group (i.e., ECC word) without exposing this data group to uncorrectable conditions should a chip kill arise. Fig. 2 depicts the block diagram of such a paging store which consists of a controller section driving multiple basic storage modules (BSMs) which contain groups of memory array elements.

Fig. 1 depicts a transfer interval which is repeated across the memory elements until the record is completed. It should be noted that in this configuration 8 elements are repeated; however, the processing of this data is modified to wait until it has accumulated all the bytes resulting from an array access before processing thru ECC. This results from the fact that the page buffer's performance is greater than the data transfer rate. Thus, the Full Page Buffer can effectively distribute the data bits from a given transfer (i.e., one chip's output across different ECC words) by selectively grouping these into different locations across the memory selection interval.

This selected group results in waiting an access penalty before processing by the ECC logic to accommodate the bytes of data associated with the selected data groups. This penalty should not affect performance b...