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Interlaced Data Regeneration for Memory Refresh

IP.com Disclosure Number: IPCOM000052528D
Original Publication Date: 1981-Jun-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Aichelmann, FJ: AUTHOR [+3]

Abstract

This is a technique for enabling an electronic data processing system t synchronize to a memory array without incurring any interruption for periodic refresh.

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Interlaced Data Regeneration for Memory Refresh

This is a technique for enabling an electronic data processing system t synchronize to a memory array without incurring any interruption for periodic refresh.

In memory systems engaged in transfers of large blocks of data, it is desirable to complete such transfers without incurring any overhead for memory refresh. This provides the use of an electronic data processing system with the highest memory availability and best performance.

Fig. 1 shows a typical block diagram of a memory system composed of multiple memory array elements (1-N). The memory timing and control section controls the regeneration (REGEN), selection and processing of data between memory and the processor. As a result, the memory timing and control must schedule the periodic refresh such that once transmission starts, no interrupts are incurred. This is achieved by grouping the regenerations such that alternate data and regeneration cycles occur. Each memory element (1-N) has an associated buffer shift register. The buffer shift register must receive enough data bits during each cycle to sustain a synchronous transfer rate to or from the processor.

Fig. 2 shows the results of this buffering by interlacing alternate data and regeneration cycles across the data transmission. Also shown is a TS and TA cycle used on initial start-up. The TS cycle is used to synchronize to the user processor, while the TA cycle is used to cover the initial or first acc...