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Browse Prior Art Database

Measurement of I/O Signal Levels in a Multi Technology Large Scale Integrated Machine

IP.com Disclosure Number: IPCOM000052534D
Original Publication Date: 1981-Jun-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 57K

Publishing Venue

IBM

Related People

Falcoz, A: AUTHOR

Abstract

This proposal is related to the probing of multi-technology logic level in a digital machine and the detection of marginal conditions.

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Measurement of I/O Signal Levels in a Multi Technology Large Scale Integrated Machine

This proposal is related to the probing of multi-technology logic level in a digital machine and the detection of marginal conditions.

The cards under test, one of which is schematically represented in Fig. 1, are connected to the board via a bottom extender card through a bottom connector and to the upper interposer via a top extender through a top connector. In the top and bottom extender cards, the I/O pins of the card under test are connected to the I/O pins of the top connector (TC) and bottom connector (BC) of the top extender card and bottom extender card through lines, only three of which 1, 2, 3 are shown.

Each extender card comprises a device which, in connection with a computer, allows the test to be performed.

This device, which comprises a module 1 and a connector 2, is represented in Fig. 2.

All I/O lines, such as 1, 2, 3, are systematically wired to the + inputs of analog comparators C, and all the - inputs are tied together and driven by a digital-to- analog converter (DAC).

The outputs of these comparators may be parallel loaded in a shift register (SR), and shifted out by a clock signal. The inputs of the DAC are driven through the SR.

The control signals and output SCAN OUT of the SR communicate with a computer. A SCAN IN pattern is shifted into SR by the computer, to set up converter DAC with the output level of the technology. A parallel load and dump into S...