Browse Prior Art Database

Three Clock Master Latch

IP.com Disclosure Number: IPCOM000052537D
Original Publication Date: 1981-Jun-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Beranger, H: AUTHOR [+2]

Abstract

Shown above is a master latch which is controlled by three clock pulses in order to reduce the complexity of the latch design.

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Three Clock Master Latch

Shown above is a master latch which is controlled by three clock pulses in order to reduce the complexity of the latch design.

The latch is controlled by the following clock pulses: +Ci with one of the clock pulses Cl...Cn active at a time, +OC which is the OR result of the Cl to Cn clock inputs, and -NC which is the NOR result of the Cl to Cn clock inputs.

Transistors T2 and T3 are the latch cross-coupled transistors. With each ith input are associated transistor TOi, resistor ROi and diode SBDi. Multiplexing is done by dotting the collectors of the transistors TOl to TOn.

The negative NC clock enables the transfer of the input data Di. If the data is 1, transistor TOi is off, transistor Tl turns on, and the output OUT turns to I. If the data is O, transistor TOi turns on, and transistor T1 cannot turn on. When transistor T2 receives the positive clock OC, transistor T2 is off and transistor T3 may only be on at that time, forcing a 0 level on output OUT.

The positive OC clock enables the data writing by suppressing the latch loop. Transistor T2 is off until the data has been written. Clock pulse OC must then fall fast enough with respect to pulse Ci and NC to hold the latch in its new state 1.

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