Browse Prior Art Database

Reference Voltage Generator

IP.com Disclosure Number: IPCOM000052550D
Original Publication Date: 1981-Jun-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Berger, HH: AUTHOR

Abstract

This generator generates a reference voltage which is automatically set to a favorable minimum value and applied to the base of multicollector transistors used as load elements in digital circuits.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 53% of the total text.

Page 1 of 2

Reference Voltage Generator

This generator generates a reference voltage which is automatically set to a favorable minimum value and applied to the base of multicollector transistors used as load elements in digital circuits.

PNP transistors T21 to T2n are used as load elements for the current supply of inverting NPN transistors T11 to T1n which may form part of a merged transistor logic (MTL/I/2/L) or a Schottky transistor logic (STL), for example. A total current I is supplied in parallel to transistors T21 to T2n which have a common base potential, reference voltage V(ref), so that the currents I0 are distributed to transistors T11 to T1n via the separate collectors of the former transistors.

Reference voltage V(ref) is generated by means of a circuit comprising a PNP transistor T20, an NPN transistor T3 and a Schottky diode D.

For keeping transistors T21 to T2n unsaturated, thus preventing an effective reduction of the current amplification of NPN transistors T11 to T1n and additional charge storage, reference voltage V(ref) at the base of the former transistors should be of adequate magnitude (higher than +100 mV). However, reference voltage V(ref) must not be unduly high, as this would increase the current tolerances and necessitate a higher operating voltage V (increased power requirements) to obtain relatively favorable tolerances.

The generator is designed in such a manner that PNP transistor T20, having the same favorable tracking characteristics as parallel PNP transistors T21 to T2n, is connected in parallel to the latter. Transistor T20 is connected to NPN transistor T3 in accordance with the equivalent circuit diagram of an SCR; i.e., it can be merged with T20 in a monolithic layout. A high...