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FET Short Pulse Driver

IP.com Disclosure Number: IPCOM000052551D
Original Publication Date: 1981-Jun-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Haug, W: AUTHOR [+2]

Abstract

A FET (field-effect transistor) true driver is proposed, the output voltage of which stays at the VH-level for a short controllable time and subsequently decays to zero at a controlled rate. As the rising edge of the input pulse generates the rising edge of the output pulse, the decay of the latter is initiated by a second pulse at a rate controlled by the impedance of a FET.

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FET Short Pulse Driver

A FET (field-effect transistor) true driver is proposed, the output voltage of which stays at the VH-level for a short controllable time and subsequently decays to zero at a controlled rate. As the rising edge of the input pulse generates the rising edge of the output pulse, the decay of the latter is initiated by a second pulse at a rate controlled by the impedance of a FET.

Fig. 1 is the circuit diagram of the FET short pulse driver, and Fig. 2 is the timing diagram. The short pulse driver operates as follows: When input pulse I is up, FET 3 is conductive, connecting the gate of FET 4 to ground, thus inhibiting FET 4. FET 5 is conductive, charging the gates of FETs 6 and 7 which are also conductive. Output node 0 of the short pulse driver is at down level. When input pulse I rises while pulse A is still up, pulse A is transmitted via FET 1 to the gates of FETs 8 and 9, making them conductive. Pulse A also charges capacitor C. Via FET 2, this pulse is also transmitted to the gate of FET 4 of a delay stage with FETs 2, 3, 4 and 5. Via FET 4, the gates of FETs 6 and 7 are discharged to ground, making the latter non-conductive. This causes the gates of FETs 8 and 9 to bootstrap above VH, allowing node O to be rapidly charged to VH potential via FET 9.

The width of output pulse O without FETs 10, 11 and 12 provided at the output of the driver corresponds to the width of input pulse I. FET 10, through which output node O can be discharged, perm...