Browse Prior Art Database

BSM Error Handling

IP.com Disclosure Number: IPCOM000052554D
Original Publication Date: 1981-Jun-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Blum, A: AUTHOR

Abstract

When a processing unit (PU) addresses a basic storage module (BSM) in main storage (MS) for a write operation, a transfer error may occur. This error is signalled to the PU via an error line, initiating a retry operation or a stop. In multiprocessing machines it was necessary for the addressing PU to wait for an acknowledgment signal indicating an error-free operation. Release of the connection to the BSM by the addressing PU before the occurrence of the acknowledgment signal made it impossible to associate a possible error with a specific PU.

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BSM Error Handling

When a processing unit (PU) addresses a basic storage module (BSM) in main storage (MS) for a write operation, a transfer error may occur. This error is signalled to the PU via an error line, initiating a retry operation or a stop. In multiprocessing machines it was necessary for the addressing PU to wait for an acknowledgment signal indicating an error-free operation. Release of the connection to the BSM by the addressing PU before the occurrence of the acknowledgment signal made it impossible to associate a possible error with a specific PU.

This waiting period is avoided by the arrangement shown in the figure. When a write access to MS is decoded in the PU, the respective output signal from the OP-REG sets a latch LT coincident with a timing pulse from a timing ring T. The PU does not wait for a signal indicating an error-free transfer operation but continues with other micro instructions in the next cycle. In an error-free operation, the BSM BUSY signal disappears after an appropriate transfer time, and latch LT is reset by AND circuit 3 controlled by a timing pulse from the T-ring. If an error occurs during the transfer time, LT is still set, and AND circuit 5 generates a TRANSFER ERROR output signal, initiating appropriate PU action. As the data to be stored in MS are still available in interface register 1 connected to a similar interface register 2 in the BSM (both registers including a data and a command part), a retry operation can be...