Browse Prior Art Database

Digital Clock Extraction Circuit

IP.com Disclosure Number: IPCOM000052607D
Original Publication Date: 1981-Jun-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Marks, LV: AUTHOR [+3]

Abstract

A digital clock extraction circuit is provided for extracting a receive clock from a phase-encoded receive data signal. The extracted clock can be used to demodulate data received on a serial interface, to sample and deserialize the data, and to provide binary data. This digital clock extraction circuit provides increased noise immunity.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 64% of the total text.

Page 1 of 2

Digital Clock Extraction Circuit

A digital clock extraction circuit is provided for extracting a receive clock from a phase-encoded receive data signal. The extracted clock can be used to demodulate data received on a serial interface, to sample and deserialize the data, and to provide binary data. This digital clock extraction circuit provides increased noise immunity.

In Fig. 1 a transition on receive data is detected by flip-flop FF1 when clocked by the internal oscillator signal. Because the receive data signal is asynchronous with respect to the internal oscillator, a simultaneous transition of both signals causes flip-flop FF1 to go into oscillation. This oscillation situation is resolved by flip-flops FF2 and FF3 which detect a transition or an oscillation in flip-flop FF1. When either FF2 or FF3 is set, a reset pulse is generated and passed via OR gate 20, AND gate 40 and OR gate 50 to counter 30. This reset pulse synchronizes counter 30 to the receive data.

Prior to synchronism, any transition of receive data synchronously resets the 2N state counter 30. Data is sampled at Count N, and the next data transition is expected at Count 2N. The internal oscillator clock is 2N times the receive data frequency.

After synchronism has occurred, for example, after receipt of a special character, or start-of-message code, the noise immunity feature of this circuit is enabled by the sync line going to AND gates 60 and 70. At the same time, AND gate 40 disables the pr...