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Virtual Address Translation Speedup Circuitry

IP.com Disclosure Number: IPCOM000052608D
Original Publication Date: 1981-Jun-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Voss, DF: AUTHOR

Abstract

The virtual address translation speedup circuitry is an improvement ove the speedup circuitry in U. S. Patent 4,170,039. The virtual address to be translated is contained in virtual address register 10. The virtual address includes bits 1-P inclusive. Of these bits, bits M-N are used as an address for simultaneously addressing translation tables 20 and 30. Tables 20 and 30 contain address translation candidates and associated main storage addresses.

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Virtual Address Translation Speedup Circuitry

The virtual address translation speedup circuitry is an improvement ove the speedup circuitry in U. S. Patent 4,170,039. The virtual address to be translated is contained in virtual address register 10. The virtual address includes bits 1-P inclusive. Of these bits, bits M-N are used as an address for simultaneously addressing translation tables 20 and 30. Tables 20 and 30 contain address translation candidates and associated main storage addresses.

The address translation candidates VA1 and VA2 are simultaneously read from the translation tables 20 and 30, respectively. The address translation candidates include bits 1-L. These bits are applied to AND circuits 60 and 65, respectively. A subgroup K-L bits of the bits 1-L from each address translation candidate VA1 and VA2 are applied to precompare circuits 25 and 35 which also receive as inputs K-L bits from virtual address register 10. The output of precompare circuit 25 is applied to AND circuits 40 and 50, and the output of precompare circuit 35 is applied to AND circuits 40 and 55. AND circuit 40 functions to determine if the K-L bits from VA1 and VA2 both compared equal to the K L bits from register 10. In the event both compared equal to the K-L bits from register 10, AND circuits 51 and 56 would be conditioned whereby AND circuit 51 would pass a T1 signal via OR circuit 52 to condition AND circuits 60 and 75. AND circuit 60 is responsive to pass the VA1 translation candidate to compare circuit 70 which compares the 1-L bits of VA1 with the 1-L bits from register 10. If they compare equal, a Start Storage Access signal i...