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Technique for Developing Multiple Test Points Using a Single Input Gate

IP.com Disclosure Number: IPCOM000052610D
Original Publication Date: 1981-Jun-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 4 page(s) / 109K

Publishing Venue

IBM

Related People

Henning, LR: AUTHOR [+3]

Abstract

With the advent of large-scale integration (LSI) technologies, an incre quantity of logic may be packaged at the first level. The logic package must be tested when it is manufactured. The increased testing problem for sequential logic may be reduced if it is properly considered during the design phase.

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Technique for Developing Multiple Test Points Using a Single Input Gate

With the advent of large-scale integration (LSI) technologies, an incre quantity of logic may be packaged at the first level. The logic package must be tested when it is manufactured. The increased testing problem for sequential logic may be reduced if it is properly considered during the design phase.

Experience has shown that it is desirable to have a means of initializing (setting or resetting) counters and latches in addition to the normal functional set or reset. In some LSI families, the D-C trigger unit has both a set and a reset input. One or both of these inputs may not be used functionally. These unused inputs are commonly tied to the inactive state. For ease in testing these inputs may be tied to a test point and exercised for test purposes only.

However, in many instances, the availability of a test input is limited by the number of I/O pins provided in present logic packages. This technique provides a method for developing a number of test signals using a functional multi-signal bus, such as a data path, gated by a single input test signal.

Fig. 1 shows a functional 8-bit data bus. This bus may have several internal data sources. For this example, two sources (Registers A and B) are used. The output data is selected, assembled, and gated out to the data path with suitable AND, OR, AND blocks followed by an off-chip driver. The data bus active signal level is down (ground) for the devices shown. Common I/O pins are used to permit input data to be applied at the same pins. Suitable gating steers the input to the several destinations, Registers C and D in this example. The source and destination logic may be the same or different; i.e., Register A equals Register C.

In Fig. 2, internal test points are added. In this system, eig...