Browse Prior Art Database

Serial Communication Line Adapter Decoder

IP.com Disclosure Number: IPCOM000052636D
Original Publication Date: 1981-Jun-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Renne, BJ: AUTHOR

Abstract

Communication lines are used to broadcast controlling data in a timed manner to a plurality of units attached to the line. Such communication lines include addressing techniques with the data. In accordance with the present article, a Programmable Logic Array (PLA) receives and decodes timing and address data to determine if data being received over the communication line is intended for the unit represented by the PLA.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 53% of the total text.

Page 1 of 2

Serial Communication Line Adapter Decoder

Communication lines are used to broadcast controlling data in a timed manner to a plurality of units attached to the line. Such communication lines include addressing techniques with the data. In accordance with the present article, a Programmable Logic Array (PLA) receives and decodes timing and address data to determine if data being received over the communication line is intended for the unit represented by the PLA.

The communication line has a data line timed by signals transmitted over a parallel clock line. Receivers transfer the communication line Signals to a PLA for serial-to-parallel conversion, decoding, and activation of the attached unit. A microprocessor in the attached unit controls other portions of the unit (not shown) in response to activation by the PLA.

A shift register constructed by personalization patterns of the PLA feeding L1, L2 latch pairs performs the serial-to-parallel conversion of the received serial data. Each serial clock pulse shifts the data to the right, as seen in the figure, from the most significant bit (MSB) at the left end of the shift register towards the least significant bit (LSB) at the right end of the shift register. Incoming data is loaded into the MSB, and the signals shifted out of the LSB are discarded. The serial data is held by latches of the PLA until the next serial clock pulse occurs. The PLA output latches feed back into the AND/OR array (not shown), which performs the shifting function and decodes the serial bytes including a synchronizing or preamble portion, the address portion and the data portion. The command is accepted for the attached unit if the preamble or synchronizing...