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Integration of High Performance Vertical PNP and NPN Transistors

IP.com Disclosure Number: IPCOM000052650D
Original Publication Date: 1981-Jun-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 5 page(s) / 173K

Publishing Venue

IBM

Related People

Isaac, RD: AUTHOR [+3]

Abstract

A compatible process is described for integrating vertical pnp and npn transistors, with specific application to MTL (Merged Transistor Logic).

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Integration of High Performance Vertical PNP and NPN Transistors

A compatible process is described for integrating vertical pnp and npn transistors, with specific application to MTL (Merged Transistor Logic).

High-performance vertical pnp transistor structures are of practical interest when they are compatible with high-performance npn transistor processes and hence can be integrated with npn transistors in circuit applications. The steps of the compatible process are as follows: 1. Form the regular vertical npn transistor, as usual, using arsenic for the top emitter doping. 2. The arsenic in the emitter of the npn transistor should have a concentration of about 1x10/19/cm/-3/. This is somewhat lower than the usual n+ emitter concentration, but it forms an excellent thin but abrupt and heavily doped base layer of the vertical pnp transistor. 3. Then form the emitter of the pnp transistor by using boron-doped p++ polysilicon, and contact the emitter of the npn transistor with n++ polysilicon. The p++ emitter drive in heat cycle should be less than or about 30 minutes at 900 degrees C. The boron from the p++ polysilicon diffuses only very slowly into the n+ base layer because of the Fermi-level-dependent diffusion characteristics. This results in very high performance npn and pnp transistors with abrupt emitter-base junction and thin base widths, the structure for which is shown schematically in Fig. 1.

In Fig. 1, the npn transistor 10 and the pnp transistor 12 are shown formed in the n epi. Details of the process would depend on the npn transistor process and the circuit application. However, it is clear that the proposed process is completely compatible with all the high-performance npn processes, be they self- aligned or non-self-aligned, since all that is required is to have the emitter arsenic doping of about 1x10/19/cm/-3/.

There are many applications of high-performance pnp that can be integrated with npn, e.g., complementary logic circuits and MTL.

In the self-aligned MTL structures the performance of the pnp transistor is one of the determining factors of performance. A high performance pnp inj...