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Run Scan Synch Circuit for Josephson Logic Chips

IP.com Disclosure Number: IPCOM000052653D
Original Publication Date: 1981-Jun-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 6 page(s) / 117K

Publishing Venue

IBM

Related People

Herrell, DJ: AUTHOR

Abstract

In Josephson logic technology, as well as in other logic technologies, circuit is required which will control the logic operation as to its normal operation (RUN) and level sensitive scan detection (LSSD) loading and unloading (SCAN). This circuit controls the RUN and SCAN operations for either a single-cycle operation (SCO) or a multiple-cycle operation (MCO).

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Run Scan Synch Circuit for Josephson Logic Chips

In Josephson logic technology, as well as in other logic technologies, circuit is required which will control the logic operation as to its normal operation (RUN) and level sensitive scan detection (LSSD) loading and unloading (SCAN). This circuit controls the RUN and SCAN operations for either a single-cycle operation (SCO) or a multiple-cycle operation (MCO).

The basic circuit is shown in Fig. 1, in which the input from room temperature electronics or a global control of the machine is provided along conductor 10. The superconducting chip 12 is connected to conductor 10 by contact 14. A self- gating AND circuit (SGA) of the type which requires only DATA, rather than DATA and DATA, is coupled to the input through the resistive network comprising R1 and R2. J1 is a Josephson device having a twin input, while J2 is a three-junction SQUID (Superconducting Quantum Interference Device). A synchronized controlling signal is provided along output conductor 16. J1 can also be a three-junction SQUID.

Fig. 2 is a simplified version of the circuit in Fig. 1, where the input I(1) is provided along the conductor 10. The control line 18 is a double-wrap control which provides twice the control current to J1 in order to switch it for a fixed input current along the control line. AC power is provided to J1 through the resistor R, there being a load resistor R(L) connected to ground.

Fig. 3 shows the threshold curves for devices J1 and J2, the MCO operation and SCO operation being indicated. Fig. 4 shows the current and voltage waveforms of the circuit and the threshold curve of J1 for multiple-cycle operation, while Fig. 5 shows the input waveforms and the threshold curves of J1 and J2 for single-cycle operation. The two modes of operation of this circuit (Fig. 2) are described below.

Multiple-Cycle Operation (a) Prior to the application of any input signal (I(10)), neither J1 nor J2 switch to the VNot equalO state (shown in Fig. 4 between t(1) and t(2)). (b) At some time (not synchronized to the AC power) the input signal rises to a level of I(1). This is not enough to switch J2. However, it will be sufficient to switch J1 since J1 has a double wrap control and therefore the effective control current rises to 2I(1)' which is approximately Phi(O)/2M for J1. This occurs at t(3) (Fig. 4). (c) The output of J1 acts as a control to J2. This biases J2 with a control of approximately 2I(1)' = Phi(O)/2M for J2. However, J2 doesn't switch because the gate level (I(1)) is well below the floor of its threshold curve. (d) Every AC power cycle that I(1) is up will lead to J1 switching. Once I(1) is applied, J1 will reswitch as the gate supply rises and the floor is traversed (t(4) in Fig. 4). (e) When I(1) is removed. J1 no longer switches as the AC power is applied (t(5) in Fig. 4).

Single-Cycle Operation
(a) Prior to a...