Browse Prior Art Database

Testing of Josephson Interferometer Circuits

IP.com Disclosure Number: IPCOM000052655D
Original Publication Date: 1981-Jun-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 3 page(s) / 69K

Publishing Venue

IBM

Related People

Herrell, DJ: AUTHOR

Abstract

When testing Josephson circuit chips containing interferometers, it is possible that the "one" input test level may place the operating point of the interferometer being tested under a lobe. Because this will not ensure that the interferometer being tested will switch, an AC signal is superimposed on a slowly varying "one" level of the primary input to the chip under test. This moves the operating point out from under a lobe in order to ensure switching. A heat switch is used to ensure that the superimposed AC signal will not appear on the "zero" test level.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 53% of the total text.

Page 1 of 3

Testing of Josephson Interferometer Circuits

When testing Josephson circuit chips containing interferometers, it is possible that the "one" input test level may place the operating point of the interferometer being tested under a lobe. Because this will not ensure that the interferometer being tested will switch, an AC signal is superimposed on a slowly varying "one" level of the primary input to the chip under test. This moves the operating point out from under a lobe in order to ensure switching. A heat switch is used to ensure that the superimposed AC signal will not appear on the "zero" test level.

Fig. 1 is a schematic of the test circuit, in which the room temperature electronics (RTE) provides the power input to the Josephson chip test adapter (CTA) via line 10. The chip under test (CUT) is connected to the CTA via the contacts 12. The CUT is comprised of a plurality of Josephson junctions 15 and a logic load R(1). The input currents I1, I2 and I3 are applied to interferometers J1, J2 and J3, respectively. Small transformers 14 are comprised of the holes 16 in the CTA ground plane. The primary winding for the transformers is the conductor 18 which carries the current I(p) (Fig. 2). The lines 20-1, 20-2 and 20- 3 are the secondaries of the transformers which are loaded with the perturbation current dI(p)/dt (Fig. 2) that is supplied to the control devices J1-J3, which are three junction SQUIDs (Superconducting Quantum Interference Devices). These perturbation currents are applied along the lines 20-1, 20-2 and 20-3.

Fig. 3 is a threshold curve for the SQUID, plotting i...