Browse Prior Art Database

Power Control Circuit

IP.com Disclosure Number: IPCOM000052708D
Original Publication Date: 1981-Jul-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 3 page(s) / 84K

Publishing Venue

IBM

Related People

Heimeier, HH: AUTHOR [+4]

Abstract

The specified power dissipation of a storage chip is influenced by many parameters and their tolerances. If it were possible to reduce or eliminate the tolerances of the parameters determining the power dissipation the cooling means required for a system could also be noticeably reduced. The power control circuit described below compensates the power dissipation caused by inevitable resistance tolerances and amounting to about 15 percent of the total power dissipation of a storage chip.

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Power Control Circuit

The specified power dissipation of a storage chip is influenced by many parameters and their tolerances. If it were possible to reduce or eliminate the tolerances of the parameters determining the power dissipation the cooling means required for a system could also be noticeably reduced. The power control circuit described below compensates the power dissipation caused by inevitable resistance tolerances and amounting to about 15 percent of the total power dissipation of a storage chip.

The basic idea is that as a result of process parameter variations, a storage chip with fast circuits (negative resistance tolerance, high power dissipation) necessitates a shorter selection time than a storage chip with slower circuits (positive resistance tolerance, low power dissipation).

The operation of the power control circuit shown in Fig. 1 will be described below by means of the time diagram of Fig. 2.

It is assumed that when a storage chip is selected, signals CWCI and CLK5 are generated from a selection signal in the clock generator. Signal CLK5 permits charging capacitor C440 via the time-determining resistor R452. If the threshold voltage set by resistors R450 and R451 is reached after a certain time, signal CWL resets latch T463/T470. Simultaneously, signal CWCO is switched to down level. By means of its leading edge, the latter signal then switches off the clock generator signals, thus terminating the internal selection phase. Latch T463/T470...