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Automatic Adjustment of Several Decentrally Generated Clock Pulse Sequences of a Computer Distributed over Several VLSI Chips

IP.com Disclosure Number: IPCOM000052714D
Original Publication Date: 1981-Jul-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 3 page(s) / 74K

Publishing Venue

IBM

Related People

Blum, A: AUTHOR

Abstract

Although there are VLSI (very large-scale integration) chips containing more than 10,000 circuits, it is not as yet possible to integrate complex, synchronously clocked data processing systems on a single chip.

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Automatic Adjustment of Several Decentrally Generated Clock Pulse Sequences of a Computer Distributed over Several VLSI Chips

Although there are VLSI (very large-scale integration) chips containing more than 10,000 circuits, it is not as yet possible to integrate complex, synchronously clocked data processing systems on a single chip.

To obtain short clock cycle times, the clock pulses on the individual communicating VLSI chips must be such that their skews, which should preferably be zero, are accurately definable and constant in time.

The clock pulses generated by a crystal oscillator are generally transferred to the individual VLSI chips via networks and logic circuits, with the delay tolerances being as much as +/- 50 percent.

To ensure minimum skews of the individual sequences, the clock pulses are presently generated on the VLSI chips proper. This permits generating clock pulse sequences at higher repetition rates.

As the skews adversely affect the performance of the circuits at very short clock intervals, it has been suggested to measure the delay tolerances of the chips during their manufacture. However, this method, which permits manufacturing processors with chips having the same delay tolerances, is very elaborate.

To automatically maintain the clock skew at a very low or predetermined value when the processor is powered on, the method described below permits controlling the clock pulse generator circuits on the chips. For this purpose, skew adjustment may be effected dynamically to suit changing operating conditions, such as changed operating voltages, temperatures or loads.

In addition to its normal functions, the VLSI chip A shown in Fig. 1 can be used as the master clock pulse generator chip, on which the other chips B, C, etc., depend. System clock A, which is the master clock of the system, is generated with an adequate basic delay DT on master chip A. By means of a fast power driver or other fast transmission means, such as capacitive coupling, the pulses of this clock are directly applied to chip B with a slight delay. Depending upon the respective counter value, the clock generator circuit on chip B generates system clock B pulses with different delays. For initialization and before the processor is started, the counter on all chips B, C, etc., is set to zero. The oscillator pulses then increment the counter, so that system clock B pulses are generated with ever longer delays delta Ti until a system clock A pulse and a system...