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System Having a Three Port Memory ALU

IP.com Disclosure Number: IPCOM000052719D
Original Publication Date: 1981-Jul-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Bartoldus, R: AUTHOR [+4]

Abstract

A three-port memory is combined with an arithmetic and logic unit (ALU) in a configuration to perform operations on data units of various widths.

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System Having a Three Port Memory ALU

A three-port memory is combined with an arithmetic and logic unit (ALU) in a configuration to perform operations on data units of various widths.

A three-port memory is made up of commercially available modules. Each module has eight master/slave latches. In a write operation, the master (input) stage of any one of the latches can be accessed according to a three-bit address and loaded with one data bit. In the same cycle, the slave (output) stage of any two latches can be accessed and read according to two independent addresses. Each module provides one bit of eight storage locations, and a memory of sixteen modules provides, for example, eight storage locations of two bytes each. The array is arranged to permit writing one data byte into any one-byte location and to permit reading any two-byte locations on each memory cycle. Thus, the memory has three ports, two for data out (read) and one for data in (write).

In one system using a three-port array, the two outputs of one byte each are applied to the two inputs of an ALU. The output register of the ALU is two bytes wide and the result, which is one byte wide, is applied to one half of this register. The other half of the output register is loaded with either the output of the ALU or with the byte at one input of the ALU. One byte from the output register can be returned to the write port of the memory and one or both bytes can be transferred to other components of the data...