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Browse Prior Art Database

Source Side Decoder for an EAROS

IP.com Disclosure Number: IPCOM000052740D
Original Publication Date: 1981-Jul-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 4 page(s) / 86K

Publishing Venue

IBM

Related People

Tien, PC: AUTHOR

Abstract

A configuration for devices of an electrically alterable read-only storage (EAROS) in field-effect transistor (FET) technology provides for source side decoding to avoid routing full programming level voltages through the decoder circuitry.

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Source Side Decoder for an EAROS

A configuration for devices of an electrically alterable read-only storage (EAROS) in field-effect transistor (FET) technology provides for source side decoding to avoid routing full programming level voltages through the decoder circuitry.

In Fig. 1, storage cells 10 are shown arranged in an exemplary 3 x 3 array with drain terminals connected to a source pad 12 that is held at a programming voltage level V(P) (typically 17 V). The source terminal for each cell 10 is connected to a respective one of a set of bit lines BL through word line selection transistors 14. A particular row of the array is selected by gate signals supplied on a set of word lines WL. A control-gate level voltage V(CG) (typically 5 V for reading and 24 V for programming) is supplied from a pad 16 to the control gates of the cells 10.

A set of selection transistors 21 is located at the source end of each of bit lines BL and receive respective selection control signals X(n). From the drain end of the respective selection transistors 21, a signal path extends to a sense amplifier (not shown) and a discharge transistor 22 that is controlled by a signal phi P.

Signals X(n) for the selection transistors 21 are produced by a set of circuits of the kind indicated in Fig. 2. Whether a program or read operation is to be performed is indicated by a signal W/R set that in conjunction with a timing signal phi 3 causes a selection circuit to produce W (write) or program or R (read) waveforms (Fig. 2). The signal Y(n) (see discussion below) is high whenever the Nth bit line is selected by the bit line address T/C signals for a read operation or, for a programming operation, whenever the Nth bit line is selected, either a ""one'' or ""zero'' can be stored in the selected cell of the array. The capacitor 20 and tr...