Browse Prior Art Database

Static FET Chip Design Program

IP.com Disclosure Number: IPCOM000052742D
Original Publication Date: 1981-Jul-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 4 page(s) / 66K

Publishing Venue

IBM

Related People

Chadwick, JE: AUTHOR [+4]

Abstract

The principles are disclosed of a computer-assisted design program for static FET integrated circuits. The program performs the circuit design and electrical checking of each circuit on an FET integrated circuit chip. The sizes of the load devices and active devices are determined on the basis of user specifications. A complete DC design and AC analysis is performed which evaluates and takes account of each circuit's electrical environment.

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Static FET Chip Design Program

The principles are disclosed of a computer-assisted design program for static FET integrated circuits. The program performs the circuit design and electrical checking of each circuit on an FET integrated circuit chip. The sizes of the load devices and active devices are determined on the basis of user specifications. A complete DC design and AC analysis is performed which evaluates and takes account of each circuit's electrical environment.

A feature of the program is its ability to design NOR and NAND circuits to achieve DC down and up levels so as to ensure the propagation of true logic zero and one values. The circuits are known as Class I circuits in the program. The program has the further ability to include ""predesigned books'' in the chip design and to account for their electrical effects on the Class I designs. These books are known as Class II and Class III books. The program can perform connections of the outputs of two or more circuits to achieve complex logic functions and will automatically analyze their interactions and design each device size.

Gate select or the sizing of all load and active devices on the chip based on user specifications is accomplished by the program. The program follows an iterative procedure to produce a solution to the specified design constraints. The program computations converge to a solution, i.e., a set of device sizes which satisfy a DC design constraint and give a stable AC design. This will discuss the program flow as shown in Figs. 1A and 1B.

Beginning with step (1), resistance and capacitance constraints are computed as a function of the technology constants which are stored in the library. At step (2), the input and output capacitances for Classes II and III books are added to the net capacitance which has been computed from the digit wiring data.

At (3), the iteration procedure begins. The computations are made by net. Each circuit and LST (logic service terminal) is processed for the net before proceeding to the next net. Before the computations begin for a new iteration, a check is made at (4) to see if a solution has been reached. A solution indicates that a stable AC design has been found. This is done by comparing the output rise and fall times for the present iteration against those of the previous iteration. The difference between each rise and fall output rise time, delta TRO and delta TFO, must be either 2 ns or 2% of TRO or TFO. If this condition is met for each and every net, then a solution has been found and an iteration switch is set at
(5). Step (6) saves the output waveform data for comparison with the newly computed values.

Circuit class is determined at (7). Class I computations begin at (8) with the determination of the total net capacitance which includes the wiring capacitance, drain and internal node capacitance, and fan-in and fan-out capacitance.

Step (9) checks if this is the last iteration (i.e., if a solution has been found...