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Browse Prior Art Database

Programmable Address Configuration of Memory

IP.com Disclosure Number: IPCOM000052755D
Original Publication Date: 1981-Jul-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 3 page(s) / 54K

Publishing Venue

IBM

Related People

Avery, LW: AUTHOR

Abstract

Apparatus is provided for partitioning bulk storage into partitions having discrete address ranges where the size of each partination is programmable. This arrangement finds particular utility for using a single size of bulk storage for containing data to refresh multiple display devices having different size screens. For example, up to four display adapters could be attached to address one storage and the storage could be used to refresh two displays having 1920 characters, three screens having 960 characters or four screens having 480 characters. Any remaining storage, i.e., storage unassigned to the refresh function, is automatically accessible in another address range to be used for common tables and work space.

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Programmable Address Configuration of Memory

Apparatus is provided for partitioning bulk storage into partitions having discrete address ranges where the size of each partination is programmable. This arrangement finds particular utility for using a single size of bulk storage for containing data to refresh multiple display devices having different size screens. For example, up to four display adapters could be attached to address one storage and the storage could be used to refresh two displays having 1920 characters, three screens having 960 characters or four screens having 480 characters. Any remaining storage, i.e., storage unassigned to the refresh function, is automatically accessible in another address range to be used for common tables and work space.

The embodiment shown in the drawing has provision for five address ranges where the ending addresses for the first four ranges and the starting address for the fifth range are: ## The starting address of the first four ranges depends upon the amount of storage assigned to the ranges. In this instance, the first four partitions have a maximum range of 3K. Thus, the starting address of the first range with a maximum storage partition would be F 4 phi phi. The starting addresses for the second, third and fourth partitions would be B 400, 7400 and 3400, respectively. The addressing range for the fifth partition is the difference between the total available storage and the amount assigned to the first four partitions. The fifth partition range could extend from phi phi phi phi to phi F F F.

An 8-bit configuration register 10 and an 8-bit sum register 20 are used for determining the range for each partition. These registers are loaded under program control. They are normally loaded at initial program load time. The configuration register bits phi-1 specify the range of 1K bytes in the first partition. Similarly, bits 2-3, bits 4-5 and bits 6-7 specify the ranges for partitions 2, 3 and 4, respectively. The contents of configuration register 10 are applied to selector 15 together with decodes of bits phi-3 of memory address register (MAR) (not shown). Selector 15 provides two bits as part of an operand A in...