Browse Prior Art Database

Double Gate Bipolar Compatible N Channel Junction FET

IP.com Disclosure Number: IPCOM000052767D
Original Publication Date: 1981-Jul-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Muggli, RA: AUTHOR

Abstract

This N-channel field-effect transistor (FET) has two gate electrode diffusions arranged with a buried isolation layer for defining a shallow depth channel in an epitaxial layer in a standard bipolar transistor fabrication process without any additional process steps.

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Double Gate Bipolar Compatible N Channel Junction FET

This N-channel field-effect transistor (FET) has two gate electrode diffusions arranged with a buried isolation layer for defining a shallow depth channel in an epitaxial layer in a standard bipolar transistor fabrication process without any additional process steps.

A substrate 10 has an N+ subcollector diffusion 12 over which a P+ layer 14 is deposited. The subcollector 12 isolates the device from the substrate 10 so that the bottom gate potential at the layer 14 follows the top gate potential at a P top diffusion 16. The P top gate diffusion 16 is diffused at the same time as the NPN base diffusion for the bipolar transistors (not shown) fabricated in the above-mentioned standard process). The P+ bottom gate diffusion 14 is diffused at the same time as the bottom isolation layer 12. Bottom gate reachthrough P+ diffusion 2O is diffused at the same time as the top P+ isolation.

The channel 18, defined by the diffusion 16 and the buried layer 14, is shallow and therefore the pinch-off potential V(P) is low, as is desired. The gate- to-channel breakdown potential of an N-channel device is much larger than that of a P-channel device, and because of electron mobility the speed is faster.

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