Browse Prior Art Database

Josephson Self Gating and Circuit

IP.com Disclosure Number: IPCOM000052814D
Original Publication Date: 1981-Jul-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Gheewala, TR: AUTHOR [+2]

Abstract

A Josephson AC latch can store data in a superconducting storage loop between machine power cycles. The self-gating AND (SGA) described here detects the signal stored in the latch and generates the true and complement of that signal during the rising portion of the power supply cycle.

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Josephson Self Gating and Circuit

A Josephson AC latch can store data in a superconducting storage loop between machine power cycles. The self-gating AND (SGA) described here detects the signal stored in the latch and generates the true and complement of that signal during the rising portion of the power supply cycle.

A schematic diagram of this circuit is shown in Fig. 1, and operates in the following way: The SGA compares the current stored in the latch loop (the control lines of devices A and C) with the current in a reference junction (device B) during the power supply ramp. If there is a current in the storage loop, then devices A and C switch before the critical current of the reference junction B is reached. When device A switches, the gate current is removed from device D, preventing a complement output. When device C switches, a true output results. Further, the extra impedance due to device D in series with device B prevents it from switching, although the complement output would still be zero even if device B switched, since there is no gate current in device D.

If there is no current (a ""0'' stored) in the latch loop, devices A and C do not switch. The current through the reference junction exceeds its critical current by the time the power supply voltage reaches about 0.8 V(max). When device B switches, gate current is removed from device C. This presents a true output and causes device D to switch, giving a complementary output.

A variation of this SGA is shown in Fig. 2. In this case, the inductance of the storage loop is obtained by having two turns of the control line on device A, which is a low inductance interfer...