Browse Prior Art Database

Josephson Ground Plane Edge Junction Regulator

IP.com Disclosure Number: IPCOM000052815D
Original Publication Date: 1981-Jul-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Arnett, PC: AUTHOR

Abstract

In Josephson circuits, regulator junctions are used together with the junctions used for the logic circuits. However, if the same current density is used in the regulator junctions as is used in the logic junctions, the area required for the regulators is unnecessarily large. In order to avoid this, the Nb ground plane is used as a base electrode for edge junction regulators, the regulator current density then being independent of the logic current density. Independent control of the current density would come primarily from control of the edge angle, a steeper edge angle giving a higher current density. The tunnel oxidation and counterelectrode steps could be common with the logic junctions.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 68% of the total text.

Page 1 of 2

Josephson Ground Plane Edge Junction Regulator

In Josephson circuits, regulator junctions are used together with the junctions used for the logic circuits. However, if the same current density is used in the regulator junctions as is used in the logic junctions, the area required for the regulators is unnecessarily large. In order to avoid this, the Nb ground plane is used as a base electrode for edge junction regulators, the regulator current density then being independent of the logic current density. Independent control of the current density would come primarily from control of the edge angle, a steeper edge angle giving a higher current density. The tunnel oxidation and counterelectrode steps could be common with the logic junctions.

The affected steps in the process might be: (1) Anodize the ground plane.
(2) Pattern the ground plane including the regulators with reactive ion etching, producing steeper edges than will be used for the logic devices. (3) Protect junction edges with photoresist in intermediate steps. (4) Open edges at the tunnel oxide step for cleaning and oxide growth. (5) Deposit M3 counterelectrode layer. (6) Complete the vertical structure (M4 metallization, etc.).

The ground plane regulator has the additional advantage of being in close thermal contact with the Si substrate. Not only are there fewer boundary layers but the Kapitza resistance is expected to be less for niobium-silicon dioxide than for lead-silicon dioxide.

The design of th...