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Dwell Time Technique for AC Power of Josephson Circuits

IP.com Disclosure Number: IPCOM000052818D
Original Publication Date: 1981-Jul-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Herrell, DJ: AUTHOR

Abstract

In Josephson circuitry powered by an AC waveform, it can be the situation that the Josephson devices stay in their voltage state when the power supply waveform changes polarity, rather than resetting. This phenomenon is called punchthrough, and is an undesirable event. In order to solve this problem, it has been previously proposed to provide a dwell time in the AC waveform near the zero crossing of the waveform. This article describes a specific technique to provide a dwell time in which the Josephson regulator junctions are placed in series with the AC power supply, while a current dump is placed in parallel with the AC supply.

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Dwell Time Technique for AC Power of Josephson Circuits

In Josephson circuitry powered by an AC waveform, it can be the situation that the Josephson devices stay in their voltage state when the power supply waveform changes polarity, rather than resetting. This phenomenon is called punchthrough, and is an undesirable event. In order to solve this problem, it has been previously proposed to provide a dwell time in the AC waveform near the zero crossing of the waveform. This article describes a specific technique to provide a dwell time in which the Josephson regulator junctions are placed in series with the AC power supply, while a current dump is placed in parallel with the AC supply.

Fig. 1 shows a conventional scheme for providing an AC power waveform, while Fig. 2 shows the waveforms produced by the circuit of Fig. 1. Here, the Josephson logic gates are represented by the resistor R loading the regulator, which is comprised of n Josephson junctions J(1), ..., J(n). The AC power supply 10 provides a current which splits into a portion i(2) flowing through the regulator and i(1) to the logic gates. As is apparent from Fig. 2, current i(1) does not have a dwell time (i.e., smaller slope) near the zero crossing of the waveform.

Fig. 3 shows a circuit which will provide a dwell time D in the current waveform i(5) delivered to the logic gates R. Here, the AC power supply 10 is connected in series with the regulator gates J(1), ...,J(n), and a current dump comprising resistor R1 is in parallel. A control line 12 is used to suppress I(m)(0) of Josephson devices J. Fig. 4 shows a composite I-V curve for the circuit of Fig. 3, where delta I(2) = delta I(...