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Programmed Logic Array

IP.com Disclosure Number: IPCOM000052844D
Original Publication Date: 1981-Jul-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 25K

Publishing Venue

IBM

Related People

Kraft, WR: AUTHOR [+4]

Abstract

An arrangement is described which increases the performance of PLAs (programned logic arrays) in data processing systems by putting a state register 3 between the AND array 1 and 0R array 2 of the PLA.

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Programmed Logic Array

An arrangement is described which increases the performance of PLAs (programned logic arrays) in data processing systems by putting a state register 3 between the AND array 1 and 0R array 2 of the PLA.

The state register 3 has a latch (not shown) between each corresponding pair of product lines 4a and 4b to isolate arrays 1 and 2 so that they may be operated in an overlapped fashion, thereby improving register 3 between the AND array 1 and OR array 2 of the PLA.

The state register 3 has a latch (not shown) between each corresponding pair of product lines 4a and 4b to isolate arrays 1 and 2 so that they may be operated in an overlapped fashion, thereby improving overall PLA system speed.

The AND and OR arrays function as they would in any PLA design. The state register 3 receives control data on product lines 4a from array 1, and, on command from the strobe line 5, stores this data for application to array 2 via product lines 4b. Once the output data from array 1 is latched up by register 3, the AND array is free for other functions, most important of which is the preparation of the next set of control data for product lines 4a. In effect, the operation of the AND array is one step ahead of the 0R array, thereby functioning in an overlapped manner. The apparent time required to pass control data through the entire PLA is reduced by allowing the AND array to function while the OR array is still busy.

The state register 3 may be provided with...