Browse Prior Art Database

Programmable Digital Delay Test Circuit

IP.com Disclosure Number: IPCOM000052849D
Original Publication Date: 1981-Jul-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 58K

Publishing Venue

IBM

Related People

Maiden, DW: AUTHOR [+3]

Abstract

The circuit is applicable in the field of instruments and/or test tools used in the testing and/or evaluation of computer-based products. The intent of the circuit is to measure or influence timing relationships of computer interfaces at the hardware level.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 53% of the total text.

Page 1 of 2

Programmable Digital Delay Test Circuit

The circuit is applicable in the field of instruments and/or test tools used in the testing and/or evaluation of computer-based products. The intent of the circuit is to measure or influence timing relationships of computer interfaces at the hardware level.

The circuit works on the principle of using loadable count-down binary counters to time or delay a particular response. The timing parameter can be set by loading a fixed frequency source. The circuit is shown in detail in the figure.

The latches 1 are used to hold the binary count value and are loaded asynchronously by the testing device. The testing device can determine if the circuit is going to be used to generate a delay or to time a response by making +ENABLE DELAY or +ENABLE TIMING inputs active, respectively. The positive edge-clock J-K flip-flop 2 and NAND gate 3 are used to synchronize the fixed frequency oscillator 4 to decrement the positive edge clocked counters 5.

To generate delays, a channel interface signal makes the +INPUT DELAY pulse active, thereby making the +START COUNT pulse output of OR circuit 12 active. This action fires the edge triggered single-shot 6, loading the counters (not shown). The +START C0UNT pulse is delayed at delay 7 to allow loading of the counters, and it enables the synchronizing and count pulse network 2, 3 and
4. When the counter 5 counts down to zero, the +CARRY line becomes active. This action clocks D flip-flop 8, making the +DELAY...